The invention relates to reliability enhancement processes, and more particularly, to a reliability enhancement process for packages having an integrated circuit (“IC”) mounted on a printed wiring board (“PWB”).
Moderate to high power original-equipment-manufacturer (“OEM”) perimeter pattern IC's such as perimeter pattern ball grid array (“BGA”) and thin small-outline packages (“TSOP”) generate a large amount of heat during operation. Typically these OEM IC's are mounted on a PWB at several solder joints. The large amount of heat typically leads to substantial thermal gradients or differences between the IC's substrate portion and the PWB. As a result, the PWB is also used as a primary heat sink. However, not only do high junction temperatures degrade the reliability of the package, but the differences in the thermal coefficient of expansion also reduce the life of the solder joints. For example, the difference in thermal expansion between the semiconductor component and the PWB is usually at least a factor of 2. That is, for every degree of temperature change, the PWB expands twice as much as the semiconductor component, which then creates mechanical stress.